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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM8A10/D
Advance Information
MCM8A10
PIN ASSIGNMENT TOP VIEW 72-LEAD SIMM - CASE TBD
A1 VSS A3 A5 A7 VCC A9 D0 VSS W1 Q1 A11 VCC DAISY D2 VSS W3 Q3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 A0 A2 VCC A4 A6 VSS A8 Q0 W0 VCC D1 A10 VSS DAISY Q2 W2 VCC D3
1M x 8 Bit Fast Static RAM Module
The MCM8A10 is an 8M bit static random access memory module organized as 1,048,576 words of 8 bits. The module is offered in a 72-lead single in-line memory module (SIMM). Eight MCM6227B fast static RAMs, packaged in 28-lead SOJ packages are mounted on a printed circuit board along with eight decoupling capacitors. The MCM6227B is organized as 1,048,576 words of 1 bit. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM8A10 is equipped with a chip enable (E) and eight separate write enable (W0 - W7) inputs, allowing for greater system flexibility. * * * * * * * Single 5 V 5% Power Supply Fast Access Times: 15 ns Three-State Outputs Fully TTL Compatible High Board Density SIMM Package Bit Operation: Eight Separate Write Enables, One for Each Bit High Quality Six-Layer FR4 PWB with Separate Internal Power and Ground Planes
PD1
38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
PD0 VSS PD2 D4 VSS W5 Q5 A20 VSS A18 A16 A14 VCC A12 D6 VSS W7 Q7
PIN NAMES
A0 - A19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Inputs W0 - W7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Enables E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable D0 - D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Inputs Q0 - Q7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Outputs PD0 - PD2 . . . . . . . . . . . . . . . . . . . . . . . . . Package Density DAISY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pins Single Net VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground For proper operation of the device, VSS must be connected to ground.
VCC Q4 W4 VCC D5 A21 A19 VCC A17 A15 VSS A13 Q6 W6 VCC D7 E
This document contains information on a new product. Specifications and information herein are subject to change without notice. 10/30/96
(c) Motorola, Inc. 1996 MOTOROLA FAST SRAM
MCM8A10 1
FUNCTIONAL BLOCK DIAGRAM 1M x 8 MEMORY MODULE
A0 - A19 E W0 D0 Q0 A0 - A19 E W D Q 1M x 1 W1 D1 Q1 A0 - A19 E W D Q 1M x 1 W2 D2 Q2 A0 - A19 E W D Q 1M x 1 W3 D3 Q3 A0 - A19 E W D Q 1M x 1
A0 - A19 E W4 D4 Q4 W D Q 1M x 1 PD0 -- Open PD1 -- VSS PD2 -- Open W5 D5 Q5
A0 - A19 E W D Q 1M x 1 W6 D6 Q6
A0 - A19 E W D Q 1M x 1 W7 D7 Q7
A0 - A19 E W D Q 1M x 1
MCM8A10 2
MOTOROLA FAST SRAM
TRUTH TABLE
E H L L W X H L Mode Not Selected Read Write I/O Pin High-Z Dout High-Z Cycle -- Read Write Current ISB1, ISB2 ICCA ICCA
NOTE: H = High, L = Low, X = Don't Care
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Tstg Value - 0.5 to 7.0 - 0.5 to VCC + 0.5 20 8.8 - 10 to + 85 0 to + 70 - 55 to + 150 Unit V V mA W C C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns). ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width 20 ns). Symbol VCC VIH VIL Min 4.75 2.2 - 0.5* Max 5.25 VCC +0.3** 0.8 Unit V V V
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH, Vout = 0 to VCC) AC Active Supply Current (Iout = 0 mA, VCC = max) AC Standby Current (VCC = max, E = VIH, f fmax) CMOS Standby Current (E VCC - 0.2 V, Vin VSS + 0.2 V or VCC - 0.2 V, VCC = max, f = 0 MHz) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) ICCA ISB1 ISB2 VOL VOH Min -- -- -- -- -- -- 2.4 Max 1 1 920 320 40 0.4 -- Unit A A mA mA mA V V
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Characteristic Input Capacitance Address Inputs E W D, Q Symbol Cin Typ 42 50 10 10 Max 58 74 13 13 Unit pF
Input and Output Capacitance
Cin, Cout
pF
MOTOROLA FAST SRAM
MCM8A10 3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1a
READ CYCLE TIMING (See Notes 1 and 2)
MCM8A10-15 Parameter P Read Cycle Time Address Access Time Enable Access Time Output Hold from Address Change Enable Low to Output Active Enable High to Output High-Z Symbol S bl tAVAV tAVQV tELQV tAXQX tELQX tEHQZ Min 15 -- -- 5 5 0 Max -- 15 15 -- -- 6 Unit Ui ns ns ns ns ns ns 5, 6, 7 5, 6, 7 4 Notes N 2, 3
NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. At any given voltage and temperature, tEHQZ max is less than tELQX min, both for a given device and from device to device. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E VIL).
+5V RL = 50 OUTPUT Z0 = 50 VL = 1.5 V 480 OUTPUT 255 5 pF
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
(a)
(b)
Figure 1. AC Test Loads
MCM8A10 4
MOTOROLA FAST SRAM
READ CYCLE 1 (See Notes 1, 2, and 8)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
READ CYCLE 2 (See Note 4)
tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tELQX Q (DATA OUT) HIGH-Z tAVQV tELICCH DATA VALID tEHICCL tEHQZ
ICC SUPPLY CURRENT ISB
MOTOROLA FAST SRAM
MCM8A10 5
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM8A10-15 Parameter P Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Data Valid to End of Write Data Hold TIme Write Low to Data High-Z Write High to Output Active Write Recovery Time Symbol S bl tAVAV tAVWL tAVWH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 15 0 12 12 7 0 0 5 0 Max -- -- -- -- -- -- 6 -- -- Unit Ui ns ns ns ns ns ns ns ns ns 4, 5, 6 4, 5, 6 Notes N 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
WRITE CYCLE 1 (W Controlled See Notes 1 and 2)
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tDVWH DATA VALID tWHQX tWHDX tWHAX
MCM8A10 6
MOTOROLA FAST SRAM
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM8A10-15 Parameter P Write Cycle Time Address Setup Time Address Valid to End of Write Enable to End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Recovery Time Symbol S bl tAVAV tAVEL tAVEH tELEH, tELWH tWLEH tDVEH tEHDX tEHAX Min 15 0 12 10 12 7 0 0 Max -- -- -- -- -- -- -- -- Unit Ui ns ns ns ns ns ns ns ns 4, 5 Notes N 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high-impedance state. 5. If E goes high coincident with or before W goes high, the output will remain in a high-impedance state.
WRITE CYCLE 2 (E Controlled See Notes 1 and 2)
tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX Q (DATA OUT) HIGH-Z tELWH tEHAX
ORDERING INFORMATION
(Order by Full Part Number) MCM 8A10 XX XX
Motorola Memory Prefix Part Number Full Part Number -- MCM8A10SG15
Speed (15 = 15 ns) Package (SG = Gold Pad SIMM)
MOTOROLA FAST SRAM
MCM8A10 7
PACKAGE DIMENSIONS
72-LEAD SIMM CASE TBD
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MCM8A10 8
*MCM8A10/D*
MCM8A10/D MOTOROLA FAST SRAM

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